ASML plans to widely adopt the High‑NA EUV technology next year for manufacturing chips with transistor sizes of 1.4 nm and smaller.

Short Summary

The new stage of semiconductor miniaturization requires a shift to more advanced lithography methods. In the next two years, the industry is expected to launch chip production using High‑NA EUV equipment that can achieve sizes down to 8 nm in a single pass and opens the way to 1.4 nm process nodes and less than 10 nm (DRAM).

1. Technological Capabilities of High‑NA EUV
Parameter Value
Numerical Aperture (NA) 0.55
Minimum size per pass ≤ 8 nm
Possible process nodes 1.4 nm (integrated circuits), < 10 nm (DRAM)

These specifications make the ASML Twinscan EXE:5200B and similar solutions critically important for future microelectronics technologies.

2. Key Players
Company Status of Implementation Commentary
ASML Manufacturer of High‑NA EUV First customers: Intel, Samsung, SK Hynix
TSMC Not ready for mass use Cost per system – 380 million USD; plan to phase out 1.4 nm chips
Intel In December 2023 introduced the Twinscan EXE:5200B Preparing for the 14A technology and related equipment
Samsung Electronics Received first scanner in December 2023; second this half‑year Planning to use it for Exynos 2600 (2 nm) and future Tesla processors
SK Hynix Adopting High‑NA EUV since September 2023 Already using conventional EUV lithography for DRAM (10 nm), plans to use at least five EUV layers for the 6th generation
Micron Technology Undecided on implementation timelines Possible plans for High‑NA EUV
Rapidus (Japan) Adopting 2‑nm technology; plans 1.4 nm in 2029 By 2027 should launch mass production of 2‑nm chips on Hokkaido

3. Economic Aspects
* Equipment cost – one High‑NA EUV system costs about 380 million USD.

* Switching to more expensive equipment raises product cost, ultimately affecting consumers.

* Therefore major manufacturers (TSMC, Rapidus) are cautious and plan staged implementation.

4. Expected Timelines
New ASML lithography scanners for mass production of advanced semiconductor products will become actively used in 2027–2028. Until then companies will gradually adjust their production lines, integrating High‑NA EUV into existing technology processes.

Conclusion
Transitioning to High‑NA EUV is a key step toward achieving 1.4 nm sizes and more compact DRAM. The world’s largest players have already begun preparatory work, but mass deployment is expected only in a few years due to high costs and the need to adapt production chains.