An AI agent built a complete RISC-V processor in 12 hours using only a 219-word request

Short news summary

* The startup Verkor.io used its own AI system *Design Conductor* to generate a fully working RISC‑V processor core in 12 hours.

* The resulting chip, named VerCore, is a five-stage pipeline core without cache or out‑of‑order execution. At 1.48 GHz in the ASAP7 process it scored 3261 points on CoreMark – almost as much as the 2011 Intel Celeron SU2300 mobile processor.

* The article details the pipeline architecture (fetch → decode → execute → memory access → writeback) and optimizations, including a fast Booth‑Walsh multiplier and a one‑cycle branch penalty scheme.

* The core was not fabricated on real silicon; its functionality was verified with the Spike simulator. VerCore can run uCLinux in that environment.

* The authors note that traditional high‑performance chip development costs over $400 million and takes 18 to 36 months involving hundreds of engineers, while their end‑to‑end autonomous process from specification to GDSII finished in 12 hours.

* Limitations of base language models were identified: the model sometimes “underestimates complexity” and attempts excessive changes, and when reasoning about Verilog it mistakenly treats it as a sequential language. This complicates debugging project timelines.

* Moving to serial production will require 5–10 people, and the increasing complexity of projects leads to nonlinear growth in computational demands, hindering commercial scaling.

* Verkor plans to publish source code and build scripts by the end of April and demonstrate an FPGA implementation at DAC.

Thus the startup showed how an autonomous AI agent can dramatically accelerate processor design, but questions about scalability and reliability in real production remain.